LeadStack Inc. is an award-winning, one of the nation's fastest-growing, certified minority-owned (MBE) staffing services provider of contingent workforce. As a recognized industry leader in contingent workforce solutions and Certified as a Great Place to Work, we're proud to partner with some of the most admired Fortune 500 brands in the world.
Title: Design Verification Engineer
Location: San Jose CA / Austin TX
Duration: 6+ Months
Contract W2 only (NO C2C)
Job Description:
• Define/plan/implement/execute functional verification strategy of complex System IP designs.
• Develop feature-based test plans
• Ability to delve into the details of Coherent fabric & LLC design.
• Work with DV team and designers to build verification environments.
• Develop UVM sequences, tests, scoreboards, monitors and checkers.
• Write SVA assertions. Functional and Code coverage Closure.
• Regression triaging and debug.
• Agility to work on multiple tasks/projects.
Skills And Qualifications Minimum requirements:
• BS/MS/PhD (or equivalent experience)
• 12+ years of relevant experience in Verification.
• Experience with System Verilog and UVM.
• Deep understanding of constrained randomization and the development of efficient test suites.
• Proficient in a script language like Perl or Python.
• Working knowledge of C++.
• Good knowledge of memory subsystem, including interconnect, last-level cache, coherency.
• Familiarity of Arm AMBA5 CHI, AMBA4 ACE or AXI coherent interconnect and bus protocols
• Experience with Chip2Chip, Die2Die protocols like UCI-E, C2C preferred.
• Good communication skills and ability & desire to work as a team player are a must.
If interested, please share your updated resume and the best time and number to connect over the phone. In case you are not available/interested, will appreciate if you can share it with your friends/network. Your referrals are appreciated!
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Should you have any questions, feel free to call me on 408-381-2480 or send an email on