Hi
Hope you are doing good.
We are looking for Design Verification Engineer Consultant. This is a full time as well as contract position. Please check the job description and reply to me if you are available for this position.
Title: Design Verification Engineer
Location: Bay Area, CA
Duration: Full Time/ Contract
Job Description:
• 12+ years of experience in SOC/IP/block level functional verification using System Verilog/UVM.
• Must have executed at-least 1 to 2 SoC/IP Verification projects on C++ based verification environment
• Knowledge of Ethernet PCS layer, and or OTN G709 is required.
• Strong knowledge of C++
• UVM and System Verilog added advantage.
• Must have worked on development of test plan, testbench components, verification environment, interface agents, Scoreboards.
• Understanding of complete functional verification cycle will be added advantage
• Skills to debug RTL & testbench issues, test failures.
• Experience on verification closure by closing Coverage and bug reports
• Understanding of customer dynamic environment change and adopt run time changes in schedule, design etc
Thanks and Regards,
Manish Kumar
P: 972-430-7053 Email:
Linkedin: linkedin.com/in/manishtechie14
Suite # 660 1320 Greenway Drive, Irving, TX 75038
Website: