Hi
Hope you are doing good.
We are looking for Chip Packaging Engineer. This is a full time as well as contract position. Please check the job description and reply to me if you are available for this position.
Title: Chip Packaging Engineer
Location: Mountain View, CA (Day 1 Onsite)
Duration: Full Time/ Contract
Candidate Roles and Responsibilities
• 5+ years' experience completing layouts of high pin count, multi-layer organic build-up packages using Cadence APD and SiP package design tools.
• Creating die and BGA symbols from scratch or from spreadsheet inputs
• Setting up design environment, including tech files, stack ups, and constraints
• Setting up Constraint Manager from scratch for complex packages (diff pair creaton, multiple power supplies, net and zone-specific constraints.
• Routing signals and matching length both manually and using tool features
• Design file management and documentation from initiation to final signoff
• Generation of POD
• Solid knowledge of top package suppliers design rules and basic manufacturing practices
Desired experience
• Experience with Cadence Orbit I/O
• 2.5D interposer design layout experience using Cadence SiP
• Experience with Virtuoso and/or Innovus for 2.5D interposer design
• Experience with Synopsys tools for 2.5D interposer design
• Experience writing and implementing custom scripts in Cadence tools
• Familiar with Cadence PVS
Thanks and Regards,
Manish Kumar
P: 972-430-7053 Email:
Linkedin: linkedin.com/in/manishtechie14
Suite # 660 1320 Greenway Drive, Irving, TX 75038
Website: