Job Description:
Position Overview: We are seeking an experienced Physical Design Engineer to join our team.
The ideal candidate will be responsible for the physical implementation of complex ASIC designs, ensuring they meet performance, area, and power specifications.
Key Responsibilities:
Lead the physical design flow from RTL to GDSII, including floorplanning, placement, clock tree synthesis, routing, and signoff.
Optimize designs for performance, power, and area while ensuring compliance with DRC/LVS rules.
Collaborate with RTL and verification teams to ensure design intent is met throughout the physical design process.
Conduct timing analysis and work towards achieving timing closure.
Develop and implement automation scripts to streamline design processes.
Required Skills:
Proficiency in both Synopsys and Cadence tools for physical design.
Strong understanding of physical design methodologies and best practices.
Familiarity with advanced technology nodes (e.g., 5nm, 7nm, and below).
Experience with designs ranging from small blocks to full reticle chips.
Experience:
5+ years of experience in physical design of ASICs.
Experience with end-to-end implementation of blocks with sizes up to 2M gates.
Technology Node Experience:2nm to 14nm +
Largest Die Experience:2nm to 14nm+
Sanity Check Questions:
Largest Block Taken End-to-End: Experience with blocks in the range of 1-2M gates is preferred.
Implementation Time for a 1M-Gate Block: Given frozen RTL and 11 corners, the expected implementation time is 10-15 days.
Preferred Qualifications:
MS or PhD in Electrical Engineering, Computer Engineering, or a related field.
Strong problem-solving skills and attention to detail.
Excellent communication and teamwork abilities.