Are you an experienced Principal Power Analysis Engineer with a desire to excel? If so, then TALENT Software Services may have the job for you! Our client is seeking an experienced Principal Power Analysis Engineer to work at their company in San Diego, CA.
Rate Range: $221127.00/year to $299172.00/year
Position Summary: Principal Power Analysis Engineer role responsible for estimating, analyzing, and optimizing high-volume, sophisticated, SoC platforms on groundbreaking nodes across multiple market segments including mobile, automotive, data center and networking, and IoT. This position plays a meaningful role in the development of production-quality silicon with outstanding performance and power efficiency, both in partnership with client partners and producing client's development silicon!
Primary Responsibilities/Accountabilities:
You will join a highly focused group to define and lead activities to analyze and optimize the power of our next generation compute solutions using innovative technologies, methodologies and tools.
- Lead a team focused on pre-silicon power analysis of SoC product features, from early estimation to final product validation.
- Work proactively across client's SoC and IP product teams to coordinate the power measurement and optimization of the SoC design.
- Collaborate with Architecture team to develop power modeling and estimation of world-leading SoCs.
- Drive activities for pre-silicon design power measurements throughout the SoC development cycle from early modeling, RTL analysis, to in-depth timing annotated netlist analysis.
- Collaborate with post-silicon characterization team to correlate pre-silicon estimates.
- Defining relevant metrics, visualizations and reports for analyzing power.
- Driving a culture of innovation in the team to improve power analysis methodologies.
Qualifications:
We are seeking strong technical leadership, with ability to develop accurate project plans involving multiple teams.
- Expertise in RTL and Netlist based power analysis flows.
- Expert knowledge of ASIC design dependencies on power efficiency including technology node, mixed Vt design, standard cell and memory library selection, voltage and power domain partitioning.
- Shown experience driving multiple projects and supporting junior engineers.
- Good knowledge of software use-cases and workloads and how they affect the hardware design power.
- Good understanding of ASIC physical design flows and simulation/emulation flows.
Preferred:
- Experience using tools for power analysis, power delivery, and signoff. (e.g. PowerPro, PrimePower, Redhawk, etc)
- Experience running simulation/emulation tools. (e.g. VCS, Questasim, Incisive, Veloce Strato, Palladium, Zebu, etc)
- Detailed knowledge of low-power design features and techniques, including clock and power gating, voltage/frequency scaling, and memory/logic retention.
- Python for automation and modeling.
- SoC use-case power budget decomposition to IP power budget.
- Development of SoC benchmarks for power and performance analysis.
- Experience with the correlation between pre and post-silicon power.
- Excellent presentation, interpersonal, and communication skills. Able to present at technical content inside and outside of the client.