216 Jobs Found for rtl in Cupertino
Job Title: ASIC Synthesis and STA Engineer Location: Santa Clara CA - Onsite role Job description: We are looking for senior ASIC Synthesis and STA Engineer who will be responsible to prepare SDC and run physical synthesis using Synopsys Fusion compiler for TSMC technology nodes below 5nm FinFET. Key responsibilities: Work very closely with RTL...
At Juniper, we believe the network is the single greatest vehicle for knowledge, understanding, and human advancement the world has ever known. To achieve real outcomes, we know that experience is the most important requirement for networking teams and the people they serve. Delivering an experience-first, AI-Native Network pivots on the creativit...
At Juniper, we believe the network is the single greatest vehicle for knowledge, understanding, and human advancement the world has ever known. To achieve real outcomes, we know that experience is the most important requirement for networking teams and the people they serve. Delivering an experience-first, AI-Native Network pivots on the creativity...
At Juniper, we believe the network is the single greatest vehicle for knowledge, understanding, and human advancement the world has ever known. To achieve real outcomes, we know that experience is the most important requirement for networking teams and the people they serve. Delivering an experience-first, AI-Native Network pivots on the creativity...
At Juniper, we believe the network is the single greatest vehicle for knowledge, understanding, and human advancement the world has ever known. To achieve real outcomes, we know that experience is the most important requirement for networking teams and the people they serve. Delivering an experience-first, AI-Native Network pivots on the creativit...
Job Title : Senior ASIC Physical Design Engineer Job Location: Santa Clara, CA (Hybrid) Job Description: The ASIC Physical Design Engineer will be responsible for taking ownership of the physical chip development, executing from the inception of the design (RTL or gate netlist) through the tape-out release to wafer fabrication using the latest S...