351 Jobs Found for rtl in Santa Clara
Design Verification Engineer: Design Verification Engineering Services Testbench development - System Verilog Universal Methodology ("UVM"), Python, and C tests Integration/development of C tests/Application Programming Interface ("APIs") and software build flow Integration of UVM testbenches Test development and debug, including without limit...
Please Note: To provide the best candidate experience with our high application volumes, we limit applications to a total of 10 over 6 months. Advancing the World’s Technology Together Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here...
Please Note: To provide the best candidate experience with our high application volumes, we limit applications to a total of 10 over 6 months. Advancing the World’s Technology Together Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here...
Job Details: Job Description: In Q4 2023, Intel announced Altera will be reported as a separate business unit beginning on January 1, 2024. This position is associated with that standalone business strategy and is expected to fully transition to a standalone company at some time in the future. In this role, the successful incumbent will provide th...
Job Description In Q4 2023, Intel announced Altera will be reported as a separate business unit beginning on January 1, 2024, with ongoing support from Intel. This position is associated with that standalone business strategy and is expected to fully transition to a standalone company at some time in the future. In this role, the successful incumbe...
Procurewise ID: TechM130045 Physical Design Engineer (8-15 Years Experience) Work Location - Santa Clara CA USA Max Salary Pay is 130 k - 150K -Only Full Time Number of positions - 3 Customer: TechMahindra Job Description: As a Physical Design Engineer, you will play a crucial role in the RTL to GDS flow, including Synthesis and Place & Ro...
ASIC Verification Engineer- UVM / RISC-V / System Verilog We are partnered up with a well-established Semiconductor organisation who enable state of the art perception for autonomous vehicles who are looking for Senior ASIC Verification Engineer to join their team in California on a remote basis. If this is you please continue reading below! Re...
6 to 10 years of experience in DV. Testbench development – System Verilog Universal Methodology (“UVM”), Python, and C tests Integration/development of C tests/Application Programming Interface (“APIs”) and software build flow. Integration of UVM testbenches. Test development and debug, including without limitation tests for functionality, power, p...
Lead Physical Design Engineer: Innovus, Tempus, Voltus, Calibre DRC/LVS Responsibilities: Contribute to automated design methodologies for ASIC physical design Perform ASIC physical design (synthesis, place-and-route), and sign-off (DRC/LVS) of mixed-signal SoCs Work with designers to integrate custom blocks into a digital toolflow Basic Qualifica...
Lead Physical Design Engineer: Innovus, Tempus, Voltus, Calibre DRC/LVS Responsibilities: Contribute to automated design methodologies for ASIC physical design Perform ASIC physical design (synthesis, place-and-route), and sign-off (DRC/LVS) of mixed-signal SoCs Work with designers to integrate custom blocks into a digital toolflow Basic Qualifica...